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MC10EP56, MC100EP56 3.3V / 5V ECL Dual Differential 2:1 Multiplexer
The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The device features both individual and common select inputs to address both data path and random logic applications. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAMS*
20 20 1 TSSOP-20 DT SUFFIX CASE 948E xxxx EP56 ALYW 1 20 20 1 SO-20 DW SUFFIX CASE 751D xxx A L, WL Y, YY W, WW = = = = = 1 MC100EP56 AWLYYWW
* 360 ps Typical Propagation Delays * Maximum Frequency > 3 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V * * * * * *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs Separate and Common Select Q Output Will Default LOW with Inputs Open or at VEE VBB Outputs
MC10 or 100 Assembly Location Wafer Lot Year Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP56DT MC10EP56DTR2 MC100EP56DT MC100EP56DTR2 MC100EP56DW MC100EP56DWR2 Package TSSOP-20 Shipping 75 Units/Rail
TSSOP-20 2500 Tape & Reel TSSOP-20 75 Units/Rail
TSSOP-20 2500 Tape & Reel SO-20 SO-20 38 Units/Rail 1000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
January, 2004 - Rev. 12
Publication Order Number: MC10EP56/D
MC10EP56, MC100EP56
COM_SEL
PIN DESCRIPTION
PIN SEL1 15 VCC 14 Q1 13 Q1 12 VEE 11 D0a* - D1a* D0a* - D1a* D0b* - D1b* D0b* - D1b* SEL0* - SEL1* COM_SEL* FUNCTION ECL Input Data a ECL Input Data a Invert ECL Input Data b ECL Input Data b Invert ECL Indiv. Select Input ECL Common Select Input Output Reference Voltage ECL True Outputs ECL Inverted Outputs Positive Supply Negative Supply
VCC 20
Q0 19
Q0 18
SEL0 17
16
1
0
1
0
VBB0, VBB1 Q0 - Q1 Q0 - Q1 VCC VEE
1 D0a
2 D0a
3
4
5 D0b
6
7
8 VBB1
9 D1b
VBBO D0b
D1a D1a
10 D1b
* Pins will default LOW when left open.
TRUTH TABLE
SEL0 X L L H H SEL1 X L H H L COM_SEL H L L L L Q0, Q0 a b b a a Q1, Q1 a b a a b
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Package (Top View) and Logic Diagram
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 2 kV > 150 V > 2 kV Level 1 UL 94 V-0 @ 0.125 in 140 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
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MC10EP56, MC100EP56
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 20 TSSOP 20 TSSOP 20 TSSOP 20 SOIC 20 SOIC 20 SOIC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 90 60 33 to 35 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min 50 2165 1365 2090 1365 1790 2.0 1890 Typ 61 2290 1490 Max 75 2415 1615 2415 1690 1990 3.3 150 0.5 Min 50 2230 1430 2155 1460 1855 2.0 1955 25C Typ 63 2355 1555 Max 75 2480 1680 2480 1755 2055 3.3 150 0.5 Min 55 2290 1490 2215 1490 1915 2.0 2015 85C Typ 65 2415 1615 Max 78 2540 1740 2540 1815 2115 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP56, MC100EP56
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current Input LOW Current 0.5 Min 50 3865 3065 3790 3065 3490 2.0 3590 Typ 61 3990 3190 Max 75 4115 3315 4115 3390 3690 5.0 150 0.5 Min 50 3930 3130 3855 3130 3555 2.0 3655 25C Typ 63 4055 3255 Max 75 4180 3380 4180 3455 3755 5.0 150 0.5 Min 55 3990 3190 3915 3190 3615 2.0 3715 85C Typ 65 4115 3315 Max 78 4240 3440 4240 3515 3815 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 W to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 11) Input HIGH Current Input LOW Current 0.5 Min 50 -1135 -1935 -1210 -1935 -1510 -1410 Typ 61 -1010 -1810 Max 75 -885 -1685 -885 -1610 -1310 0.0 150 0.5 Min 50 -1070 -1870 -1145 -1870 -1445 -1345 25C Typ 63 -945 -1745 Max 75 -820 -1620 -820 -1545 -1245 0.0 150 0.5 Min 55 -1010 -1810 -1085 -1810 -1385 -1285 85C Typ 65 -885 -1685 Max 78 -760 -1560 -760 -1485 -1185 0.0 150 Unit mA mV mV mV mV mV V mA mA
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP56, MC100EP56
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 14) Input HIGH Current Input LOW Current 0.5 Min 50 2155 1355 2075 1355 1775 2.0 1875 Typ 61 2280 1480 Max 75 2405 1605 2420 1675 1975 3.3 150 0.5 Min 50 2155 1355 2075 1355 1775 2.0 1875 25C Typ 63 2280 1480 Max 77 2405 1605 2420 1675 1975 3.3 150 0.5 Min 55 2155 1355 2075 1355 1775 2.0 1875 85C Typ 66 2280 1480 Max 80 2405 1605 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 13. All loading with 50 W to VCC-2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 17) Input HIGH Current Input LOW Current 0.5 Min 50 3855 3055 3775 3055 3475 2.0 3575 Typ 61 3980 3180 Max 75 4105 3305 4120 3375 3675 5.0 150 0.5 Min 50 3855 3055 3775 3055 3475 2.0 3575 25C Typ 63 3980 3180 Max 77 4105 3305 4120 3375 3675 5.0 150 0.50 Min 55 3855 3055 3775 3055 3475 2.0 3575 85C Typ 66 3980 3180 Max 80 4105 3305 4120 3375 3675 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 16. All loading with 50 W to VCC-2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP56, MC100EP56
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 19) Output LOW Voltage (Note 19) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 20) Input HIGH Current Input LOW Current 0.5 Min 50 -1145 -1945 -1225 -1945 -1525 -1425 Typ 61 -1020 -1820 Max 75 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 50 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 63 -1020 -1820 Max 77 -895 -1695 -880 -1625 -1325 0.0 150 0.5 Min 55 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 66 -1020 -1820 Max 80 -895 -1695 -880 -1625 -1325 0.0 150 Unit mA mV mV mV mV mV V mA mA
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 W to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 2 Fmax/JITTER) Propagation Delay to Output Differential D to Q, Q SEL to Q, Q COM_SEL to Q, Q Within-Device Skew (Note 22) Device to Device Skew Random Clock Jitter (See Figure 2 Fmax/JITTER) Input Voltage Swing (Differential) Output Rise/Fall Times (20% - 80%) Q, Q 150 70 250 250 250 340 340 350 50 0.2 800 120 450 450 450 100 200 <1 1200 170 150 80 270 270 270 360 340 360 50 0.2 800 130 470 470 470 100 200 <1 1200 180 150 100 300 300 300 400 400 400 50 0.2 800 150 500 500 500 100 200 <1 1200 230 ps ps mV ps Min Typ >3 Max Min 25C Typ >3 Max Min 85C Typ >3 Max Unit GHz ps
tSKEW tJITTER VPP tr tf
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. 22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs.
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MC10EP56, MC100EP56
1000 VOUTamplitude (mVpp) 5V 800 3.3 V 600 10 9 8 7 6 5 4 3 2 1 400 JITTEROUT ps (RMS)
200 1.0
Driver Device Q 50 W 50 W D
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
EEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EE
(JITTER) 0 1.5 2.0 2.5 FREQUENCY (GHz) 3.0
Figure 2. Fmax/Jitter @ 255C
Q
D Receiver Device
V TT V TT = V CC - 2.0 V
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MC10EP56, MC100EP56
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE B
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
2X
L/2
20
11
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC10EP56, MC100EP56
PACKAGE DIMENSIONS
SO-20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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MC10EP56, MC100EP56
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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